Unveiling the 'He-style Law': Xu Zhijun reveals for the first time the full story behind Huawei (华为)'s chip breakthrough

The reveal

Xu Zhijun (徐直军), a senior Huawei executive, has for the first time laid out the six‑year story behind the company’s chip turnaround, and He Tingbo (何庭波), president of HiSilicon (海思), publicly presented the underlying method at IEEE ISCAS 2026. It has been reported that He unveiled what Huawei calls the韬（τ）定律—translated by the company as the “Tao (τ) law”—a system‑level doctrine that substitutes Moore’s geometric scaling with a deliberate “time‑scaling” approach to compress signal propagation delay (τ) across device, circuit and system layers. Some observers have already dubbed the framework the so‑called “He‑style law.”

Why Huawei had to change course

The story is inseparable from geopolitics. Huawei (华为) was placed on the U.S. Entity List in May 2019 and a follow‑on application of the U.S. Commerce Department’s foreign direct product rule (FDPR) in 2020—reportedly nicknamed the “HiSilicon rule” within Washington—cut off access to advanced foundry processes. TSMC (台积电) had been producing roughly 90% of Huawei’s chips; when that supply was threatened, Huawei faced a binary choice: accept technical obsolescence or reinvent the stack. Xu says HiSilicon was told to be a “cost centre” whose survival depended on keeping Huawei alive. The result was a two‑track effort: push domestic fabs to improve process capability and re‑architect chips to be competitive on less advanced nodes.

What the Tao (τ) law actually promises

Tao (τ) law reframes the problem: if you cannot shrink transistors geometrically, shrink the time constants that govern signal travel. That means redesigning circuits, interconnects, packaging and system topology together. Central to Huawei’s work is “logic folding”—a kind of functional 3D re‑layout in which a single logical die is split and interleaved across layers so signals travel micrometers instead of millimetres, reducing buffering and latency. Huawei gave performance examples—reportedly CPU clock jumps from 2.6GHz to 3.1GHz, NPU gains of 1.4× and GPU uplifts of 30–40%—and described a three‑pronged stack (Unified Bus, near‑package optical Hi‑ONE engine, and 3D Folding). These claims, Huawei says, demonstrate how system‑level timing optimisation can offset process node gaps.

Costs, industry context and what comes next

The bill was time and engineering muscle. Huawei spent years building internal EDA tools and refactoring thousands of designs; it has been reported that the effort produced 381 chips that reached volume production. That grind distinguishes Huawei’s path from the broader industry trend—NVIDIA, AMD and Intel are leaning on chiplet, 3D packaging and heterogeneous integration, but most can still buy leading nodes from TSMC or others. Huawei’s approach was forced by sanctions; does necessity make it a blueprint others will follow? The answer matters geopolitically: Washington’s policy aimed to “buy time” against Huawei by widening the process gap, but Huawei’s counter is also a time play—just on a different axis. Time will tell whether τ‑centric engineering becomes a mainstream post‑Moore route or remains a sanction‑driven detour.