Huawei's "Tao (韬) Law" pushes chip design into true 3D — Peking University rapidly unveils a prototype EDA flow

What Huawei announced

It has been reported that Huawei (华为) has publicly framed a new chip architecture paradigm it calls the "Tao (τ) Law" — centered on "logic folding" — that moves design optimization off the 2D plane and toward stacked standard-cell reconstructions across multiple wafers. Unlike die‑to‑die stacking that assembles coarse blocks after design, logic folding slices a single module down to standard‑cell granularity and distributes those cells vertically across bonded wafer layers, reportedly using micron or sub‑micron face‑to‑face hybrid bonding to stitch critical paths in the vertical dimension.

Peking University’s "true‑3D" EDA prototype

Responding within days, Peking University (北京大学)'s School of Integrated Circuits said it has developed a prototype "true‑3D" physical‑implementation EDA tool tailored for logic folding. It has been reported that the prototype covers placement planning and detailed placement, is GPU‑accelerated to handle tens of millions of instances, and folds cross‑die wire length, hybrid‑bond terminal count and vertical thermal paths into a single differentiable optimization framework. Reportedly, system validation on open industrial designs (from ~1M to ~24.7M instances) produced about a 30% average wire‑length reduction, ~6% WNS improvement, ~12% TNS improvement and over 3% peak temperature reduction with little wire‑length penalty — results the team says will be published in full soon.

Why this matters — and what comes next

Why the sudden urgency? Because logic folding breaks assumptions built into today's "pseudo‑3D" flows, which pin whole modules to a single die and reuse largely 2D toolchains. True‑3D demands global three‑dimensional search — partitioning inside modules, cross‑die moves, and thermal and interconnect tradeoffs solved together. That is a hard software problem as much as a fabrication one. It has been reported that Peking University's effort is part of a longer‑term national push in China to develop domestic 3D‑IC methodologies and EDA horsepower — a strategic priority intensified by export controls and restrictions on advanced tooling and IP from the West. Can academic and domestic toolchains bridge the gap to commercial EDA incumbents and supply constrained foundries? The rapid prototype suggests the answer is being tested in real time.