Huawei (华为) unveils "LogicFolding" and a τ (tau) law to drive time‑centric semiconductor evolution

A new guiding principle: time, not geometry

At the IEEE ISCAS 2026 conference, Huawei (华为) engineer He Tingbo (何庭波) set out a provocative new roadmap for chips: the韬 (τ) law, which replaces traditional geometry‑based scaling with "time (τ)缩微" — shrinking signal propagation delay as the primary axis of progress. According to IT Home (IT之家), He argued that continuous reduction of end‑to‑end time constants, rather than just smaller transistors, should guide semiconductor and system evolution. Simple idea. Big implications.

LogicFolding and a multi‑level collaborative stack

Huawei introduced core techniques including LogicFolding (逻辑折叠) and a multi‑level collaborative optimization framework that spans devices, circuits, chips and systems. At the device level the focus is on cutting transistor and interconnect resistance and parasitic capacitance to minimize device τ. At the circuit level LogicFolding is said to break planar layout limits, shortening critical‑path routing and lowering RC load to boost transistor effective density and performance. At the chip level Huawei describes full‑stack co‑design — software, architecture and silicon — to tightly control instruction and data flows for higher parallelism and lower end‑to‑end time; at the system level it proposed a "Lingqu bus" (灵衢总线) to reshape interconnect protocols for unified memory addressing and native memory semantics across supernodes, aiming to slash system communication latency.

Why this matters — and what remains to be seen

The proposal is clearly shaped by hard limits in Moore’s Law and by geopolitical pressure. With U.S. export controls and restricted access to cutting‑edge foundries, Chinese firms have been pushed toward architectural and stack‑level innovations. It has been reported that Huawei claims the approach could yield high‑end chips with transistor density equivalent to a 1.4 nm process by 2031, and that its "Kirin 2026" chip is the first successful implementation of LogicFolding; these assertions are reported but not independently verified. Can clever layout and system co‑design compensate for limited node access? Huawei’s talk maps out a plausible strategy — one to watch closely as samples, benchmarks and product roadmaps (reportedly including a Mate 90 launch) begin to appear.