Huawei (华为) says Kirin 2026 is first successful use of “logical folding”; aims for full folding within a decade

What was announced

At the International Symposium on Circuits and Systems (ISCAS 2026), Huawei (华为) board member and head of its semiconductor division He Tingbo (何庭波) said the company’s upcoming “Kirin 2026” mobile SoC will be the first successful implementation of what Huawei calls logical folding technology, and that the chip delivers “substantial” performance gains. It has been reported that the Kirin 2026 is due this autumn and, following Huawei’s typical cadence, the Mate 90 series could be the first phone to ship with it.

He presented logical folding as a new design paradigm that complements — and in some ways replaces — traditional transistor scaling. Where Moore’s Law is like building a bigger house on the same plot by making bricks (transistors) ever smaller, Huawei’s so‑called “Tau (韬) law” is likened to turning a bungalow into a multi‑storey building: stacking or folding logic to increase effective density without relying solely on extreme node shrinks. Huawei reportedly projects that, by 2031, designs based on this principle could achieve transistor-density equivalents comparable to a 1.4 nm process node.

Why this matters — and the geopolitical angle

Why should Western readers care? Because China’s chip industry has been operating under significant external pressure: export controls and restrictions on advanced foundry tools have limited access to the newest process nodes from TSMC, Samsung and the like. Faced with those limits, Chinese firms are accelerating architectural and packaging innovations — logical folding, chiplets, advanced packaging — as strategic alternatives to pure node scaling. Will such approaches close the gap with leading‑edge fabs? The answer will depend on system‑level tradeoffs, ecosystem support, and toolchain maturity.

Huawei has not released technical details or benchmarks beyond He’s statement, so independent verification is pending. Reportedly, the company plans a multi‑year push toward “full folding” and even multi‑layer folding across devices, circuits and systems — a shift that, if proven at scale, would reshape how we think about performance gains in an era of constrained node progression.