Huawei (华为) unveils Die-on-Board SSDs up to 122.88TB, plans 245TB model

Lead: packaging, not new NAND

Huawei (华为) showcased a new family of high-capacity SSDs at the ID Forum 2026 in Paris, using a self-developed Die-on-Board (DoB) packaging process to deliver 61.44TB and 122.88TB enterprise SSDs, with a 245TB variant reportedly planned. The key angle: Huawei is increasing raw drive density through packaging innovation rather than by gaining access to the latest 3D NAND chips. How does that change the game for data centres and AI workloads?

What DoB means — and why it matters

DoB places more NAND die directly on the PCB, bypassing the physical stacking limits of traditional TSOP/BGA packages. Mainstream TSOP/BGA approaches typically cap at about 16 stacked dies; Huawei’s DoB reportedly supports up to 36 layers, boosting density and cutting some costly packaging steps. It has been reported that major NAND makers such as Samsung (三星) have 400‑layer-plus 3D NAND, but those chips involve U.S. technology and cannot be supplied to Huawei, prompting the company to pursue density gains at the packaging level.

Product demos and system context

At the Paris event Huawei also demonstrated OceanDisk enclosures that pair these DoB SSDs with its OceanStor Pacific arrays — one 2U chassis advertised at 1.47PB using DoB-based drives, and a 2RU OceanDisk claimed to house 36 × 61.44TB SSDs for 2.2PB raw capacity. Huawei says its AI SSD architecture integrates an AI accelerator in the controller to enable storage-compute synergy and lower data‑movement energy, and that DoB has already been scaled into commercial OceanStor Pacific and OceanDisk QLC PCIe Gen4 products.

Market and geopolitical implications

This is both a technical and strategic response to export controls: by innovating at the package and system level Huawei narrows the capacity gap with competitors that can access the latest NAND die, such as Kioxia (铠侠)–backed designs used by some Western OEMs. It has been reported that Huawei positions DoB as part of a broader Wafer‑Scale roadmap described in its 2024 "Data Storage 2030" white paper, tackling manufacturing, cross‑chip interconnect, thermal and reliability challenges to enable large‑scale commercial deployment.