Apple explains why Mac M5 chips use three different CPU core types for the first time
Apple (苹果) hardware executive Anand Shimpi and Mac product manager Doug Brooks told German magazine Mac & i why the new M5 family adopts three distinct core architectures — efficiency, performance and a new “super” core — with the M5 Pro and M5 Max marking the first use of that trio. It has been reported that the base M5 pairs efficiency and super cores, while M5 Pro and M5 Max combine the new performance core with the super core to balance single‑thread speed and multi‑thread throughput.
Architecture by role
Shimpi described the super core as “the world’s fastest CPU core” and said it is tuned specifically for peak single‑thread performance. He contrasted that with Apple’s highest‑efficiency core, which cannot match the super core’s per‑clock speed but drastically reduces power draw for background tasks. The newly introduced performance core is not merely a higher clocked efficiency core, Shimpi added; it is a bespoke microarchitecture designed to out‑perform the prior efficiency core on throughput while still improving energy use, and it is targeted at multithreaded workloads.
Product positioning and what’s next
Brooks said the three‑name scheme — efficiency, performance and super — was chosen to make each core’s role clear to users and developers. When asked whether the fused architecture used in M5 Pro and M5 Max would carry over to a future M5 Ultra, Shimpi declined to comment beyond noting Apple has only announced M5 Pro and M5 Max so far.
Why it matters
Why add a third core type now? The move lets Apple tune chips more granularly for the divergent needs of macOS workflows: long battery life and light background tasks, heavy multithreaded workloads, and peak single‑thread responsiveness. The shift also arrives amid heightened global competition over semiconductor design and supply chains, where in‑house chip differentiation has become a strategic priority for major tech firms seeking performance advantages and supply resilience.