Morgan Stanley (大摩) says the China–U.S. AI GPU gap isn’t as large as imagined — 2026 could be the turning point

A contrarian read: smaller gap, sooner inflection

It has been reported that Morgan Stanley (大摩) released a note titled “China AI GPUs — narrowing the gap with the U.S.” that makes a blunt, contrarian claim: the performance gap between China’s AI chips and U.S. GPUs is not as wide as the market assumes, and 2026 could be an industry inflection point. Why? Beyond steady technology gains, the report highlights differences in operating economics — notably lower power costs in China — which reduce the weight of raw process-node advantages when you measure performance per watt per dollar. Reportedly, capital flows matter too: China’s new generation of AI‑GPU players, including Baidu’s (百度) Kunlun (昆仑芯) and Alibaba’s (阿里) Pingtouge (平头哥), are moving toward IPOs, which could unlock scale.

Supply‑chain constraints keep the ceiling in place

Morgan Stanley’s caution is practical. China’s capacity and toolchain remain the binding constraints. SMIC (中芯国际) is the lynchpin of domestic advanced logic; the bank projects SMIC’s N+2 (~7nm) capacity rising from roughly 22k wafers/month in 2025 to about 40k in 2026 and 51k in 2027. But fabs still rely heavily on ASML’s DUV tools, and it has been reported that shortages of KLA inspection kit have forced Chinese fabs to compress testing regimes — a move that sustains output at the cost of yield. On the software side, Huada Empyrean (华大九天) holds only an estimated 1–2% global EDA share while Cadence, Synopsys and Siemens account for over 80%, and U.S. export controls on advanced EDA and GAA design tools are explicitly aimed at slowing Chinese progress toward 3nm and 2nm nodes.

From single‑chip parity to system‑level workarounds

If process parity is hard to buy, China is buying scale, packaging and architecture. Domestic firms are pursuing multi‑die advanced packaging and rack‑level designs to aggregate compute — think Huawei’s (华为) CloudMatrix 384, Alibaba’s PPU concept, or Bytedance’s 256‑accelerator rack — rather than chasing single‑die MHz or transistor counts. SMIC’s rising capex (reported around $75bn in 2023, $73bn in 2024 and estimated $81bn in 2025 across the industry) and growing domestic equipment suppliers — NAURA (北方华创), AMEC (中微公司) and SiCarrier among them — are easing bottlenecks, but structural and geopolitical risks remain. The headline is simple: the hardware gap may be smaller in practical workloads than node‑to‑node comparisons suggest, but how fast China can translate capacity, tooling and capital into reliable, large‑scale supply will depend on both domestic investment and the contours of Western export policy — 2026, it seems, will be a year to watch.